Overview
· 7+ years of experience in the area of RTL design and verification of silicon
· At Least 3+ years experience in leading LP low-power mixed-Signal SOC design preferably with RF contect [RAT1] in the design
· 7+ years of experience with FPGA architecture specification and design (Altera or XilinixXilinx) for high-speed serial protocols, including USB-SS, PCIe, SATA/SAS, DisplayPport
· Experience in leading, specifying, and work with Analog/RF team in developing, verifying, and productizing SERDES, CDR, and PLL/DLL designs
· Experience with USB 3.0, DisplayPort, PCIe, or SATA based silicon designs
· Strong background in analog/mixed-signal integrated SOC Development
· Strong Hardware design knowledge and familiarity with high speed PCB layout, signal integrity, EMC/EMI
· Strong foundation in SoC architecture, design, verification and physical implementation
· Strong analytical problem solving, and attention to details
· Knowledge of wireless, mobile, and storage domains
· Expertise in Verilog/System Verilog, C/C++/SystemC, UVM, Scripting languages like Perl/Python, etc.
· Excellent technical documentation skills
· Excellent written and verbal communication skills
· Excellent interpersonal skills, self-motivated, self-starter
· Experience in startup environment
About US Based Client
US 2nd largest Semiconductor industries is hiring for full time Design Engineers.
Interested please share updated cvs to belagalbasav@gmail.com